LHC@home

Hi Eric,

I know that you don't have much time but I thought it might be easy to implement with complier switch.

I read article on Anandtech that quoted some performance figures for newer CPU's.

For the AVX instructions there is about a 2x performance improvement vs SSE in fp64 code and AVX+FMA give a further 2x over just AVX.

Would it be easy to do an AVX/FMA binary?

Thanks Tony; no real problem and a factor of 2!.
Eric

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.......but FMA is not really possible because numerically
incompatible with non-FMA,........ :-(

I'll try and find time to test and measure SixTrack. Eric.

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No problem, just thought it could be an easy thing with complier switch.

Numeric equilivence is another matter ;)

The project seems not to enforce using the latest version, I see a lot of PNI results on hosts that would be capable of running SSE3.

I'm using a little patch on my (outdated 5.10.28) core clients so they report that my CPUs can do SSE3 but it needed a reset in order to make the hosts pull the SSE3 project application. Before the reset, my hosts did report SSE3 properly (can be seen in the sched_request) but still crunched using the PNI application.

If I remember correctly, PNI = SSE3, and the applications are also identical. Please correct if I'm wrong.

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If I remember correctly, PNI = SSE3, and the applications are also identical. Please correct if I'm wrong.

You are correct. PNI is short for Prescott New Instructions, and is exactly the same thing as SSE3.

I did a binary file compare on the older pair of Sixtrack applications (for Windows), and they were identical. I haven't repeated that with 446.03, but I expect they would be again.

oops, I thought that SSE3 came later than P4 - but I skipped that CPU type and went from Tualatin and Thoroughbred (and one Dothan) to Core2. Thanks for clearing that up.

Well we just copy the SSE3 executable to PNI. We build only
32-bit generic ia32, sse2 an sse3. Eric.

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